1. Field of the Invention
The present invention relates generally to application specific integrated circuit prototyping, and more particularly to partitioning an ASIC into multiple programmable logic devices.
2. Description of Related Art
Typically, a field programmable gate array (FPGA) was used in prototyping an application specific integrated circuit (ASIC). However, a complex ASIC does not fit into a single FPGA despite the fact that FPGA capacity has grown exponentially in recent years.
To prototype a complex ASIC design, multiple FPGAs, typically mounted on a printed circuit board, must be used. When different blocks of the ASIC are programmed in different FPGAs, the interface signals between the ASIC blocks become chip-to-chip interconnects on the printed circuit board.
FIG. 1 is a block diagram of a block-based ASIC architecture with block A 110, block B 120, and block C 130 communicating with each other via a communication block 140. Communication block 140 could be a switch fabric or a bus.
Block A 110, block B 120, and block C 130 typically share a common interface protocol to communicate with communication block 140. If, for example, communication block 140 is a PCI bus, block A 110, block B 120, and block C 130 all have the same PCI interface logic.
Unfortunately, the number of interface signals between the ASIC blocks can easily exceed the FPGA package pin count. In cases where the FPGA package pin count is sufficient, the signal routing on the printed circuit board becomes very difficult and expensive. If there is a logic error in programming one of the FPGAs, it may be necessary to redo the signal routing on the printed circuit board, which adds further delay and cost. Hence, as ASICs become more complex, the use of FPGAs to prototype an ASIC is becoming more difficult and expensive.